Tag Archives: transistors

This week’s theme at Engineer Blogs asks the authors to recount their path to “success”. What were the turning points? Who was involved? And so forth. The arc of a storyline usually tells of a protagonist that is transformed as the events unfold from beginning to end. Tiger Woods is a good example — rising prodigy, international superstar, fall from grace. Adolf Hitler is another great example — struggling artist, dictator extraordinaire, suicide. Or we can look at Barack Obama — fatherless childhood, President of the United States, Kenyan Muslim Marxist. But not everyone is blessed enough to have a sweeping story arc in their lives. Donald Trump, for example, is more of a sine wave than an arc. And for me, it’s more or less a straight line with a shallow slope. A suburban upbringing. Good at math and physics in high school. Studied engineering. Works in engineering. Continues…

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One of the most famous observations in the semiconductor industry is Moore’s Law. The “law” predicts the number of transistors on a given area of silicon will double every 18-24 months. The strive by all companies to abide by Moore’s Law has given us unparalleled increases in computing power. However, Moore’s Law has really ever only worked for digital integrated circuits. Analog circuits do not scale the same, but I’ll leave the topic to another day. Ever since Gordon Moore made his eponymous observation in the 1970s, the semiconductor industry has used this “law” as a guide in their R&D, reaching and maintaining the doubling that Moore had predicted for over 40 years now. Still, there comes a point when transistors can no longer be shrunk, when the transistor hits its fundamental physical limits. Even Moore said in 2008 that Moore’s Law is dead. There has been many predictions of…

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In my post a couple of weeks back on A Matter of Scale: Electromigration, I mentioned that once silicon features shrunk below 100nm into the world of nanotechnology, previously negligible physical phenomena now play a big role. One of those annoying phenomena is the well proximity effect (WPE). To explain how WPE affects integrated circuit designers, we have to first talk just a little bit on how PMOS transistors are created. The figure above shows the standard textbook cross-section of a silicon wafer with an NMOS and PMOS transistor side-by-side. The silicon wafer, also called the substrate, is a crystalline structure where each silicon atom shares four covalent bonds with neighbouring silicon atoms. However, it is standard in the IC industry to lightly dope the silicon wafer substrate with boron. If you remember your high school chemistry, silicon has four valence electrons and boron has only three. When boron is…

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Interview Strengths

Last week, I wrote about an interview with a disappointing candidate that was applying for a analog IC design position with FluxCorp. Although he wasn’t able to answer many questions regarding his own past designs (or alleged designs), I still thought it necessary to give him a chance by moving to more basic questions, like the transistor. In my opinion, these questions are not difficult. If one bothers to prepare for an interview like this by flipping through some old text books, these questions should be a breeze. Unfortunately, the candidate (let’s call him Mr. Flop) in question failed horribly, which illustrates a few things. First, he doesn’t know how to prepare for an interview. Second, he has not internalized undergrad material in his brain so that he can claim to be qualified to be an analog IC designer. Third, he grossly overstated his abilities on his resume. And I’m…

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