Reality vs. Virtuality
This week’s Theme Week at Engineer Blogs is dealing with cross functional engineering material. Like most mechanical engineers, I’ve had to do my fair share of other engineering disciplines, mainly civil/structural (on the small scale) and electrical (basic circuits, signal processing). Because ME, EE, and Civil are all what I would consider core engineering disciplines, I think most engineers in one of those three fields should understand the basic concepts of the other two fields. Typically, the fundamental concepts in Civil are easier to understand for a ME. (I mean, you have to know your target to make the right bomb 😀 ). Basic concepts on the EE side are a little harder to grasp because they tend to be more abstract. But if you’ve had to do any programming, you understand Paul Clarke’s underlying argument, even if you don’t get the complete package. As we divert from the core…
Pro/E, My love-hate relationship
PTC’s Pro/Engineer (now called Creo Elements), in my humble opinion, is a terrible software. I say this as someone who used to have a lot of experience with it. I started using Pro/e during my UG freshman year. During my sophomore year, I started being a TA for the class. During that year and the following 3 years, I TA’ed between 4 and 8 sections of Pro/e (and Pro/e2 and Pro/e Wildfire), to hundreds of incoming freshman, getting to the point where I was going over the design lectures and the main prof for the class only showed up for tests. In general, being a TA and pseudo-lecturer gave me some good exposure to how lectures really work in college from the other perspective and it got me over my fear of public speaking. So the intangibles associated with the position were pretty good. But man, Pro/e is a terrible…
VHDL Numeric Library Sheep
So some time back, I did a few blogs about how much I like writing VHDL and what a wonderfully language it is. I also did a bit of an intro for software engineers (don’t worry, you don’t need to read them to see where I’m going here). However, I came under a bit of criticism about what I wrote and my use of the evil STD_LOGIC_ARITH package. OK, I may not be a full-time VHDL engineer but I think there are far too many people being sheep and using the numeric library though peer pressure while not considering true engineering principles. So first off, let’s get this all straight – I class myself as a embedded electronics design engineer. My day job is all low-level electronics and microcontrollers, no FPGAs. However, I spent a few years working on a VHDL design for a Gigabit Ethernet Card where I looked…