A Matter of Scale: Moore is Dead, Long Live Moore

A Matter of Scale: Moore is Dead, Long Live Moore

One of the most famous observations in the semiconductor industry is Moore’s Law. The “law” predicts the number of transistors on a given area of silicon will double every 18-24 months. The strive by all companies to abide by Moore’s Law has given us unparalleled increases in computing power. However, Moore’s Law has really ever only worked for digital integrated circuits. Analog circuits do not scale the same, but I’ll leave the topic to another day.

Ever since Gordon Moore made his eponymous observation in the 1970s, the semiconductor industry has used this “law” as a guide in their R&D, reaching and maintaining the doubling that Moore had predicted for over 40 years now. Still, there comes a point when transistors can no longer be shrunk, when the transistor hits its fundamental physical limits. Even Moore said in 2008 that Moore’s Law is dead. There has been many predictions of Moore’s Law’s demise over the past two decades. Each time pundits predict that the transistor is close to its fundamental limit, that it has at most another factor of 2 to shrink, they are proven wrong by scientist and engineers who research better and more complex ways to shrink the transistor ever more.

Here’s a chart on the feature size of transistors. Note the logarithmic scale on the vertical axis.

As you can see, we’re now into the sub-30nm realm, and Intel has announced their 14nm node is in the R&D phase. The number at each technology node indicate the smallest feature that can be fabricated on silicon and is approximately 1/sqrt(2) the size of the previous node. A linear shrink by 1/sqrt(2)=~0.7 results in a 1/2 area shrink in two-dimensions. This continued miniaturization is astounding. To put the numbers into perspective, here’s is a comparison of the area taken by a single on-chip metal contact in 1978, and a 10-bit SRAM in 2008.

It appears the march of Moore’s Law continue unabated. So why is Moore dead?

The reason lies in leakage.

What is leakage? Let’s refer to two transistor cross-sections shown below (taken from the previous post in this series A Matter of Scale: Well Proximity Effect).

The gate terminal, G, is the control valve for the transistor. The voltage applied to terminal G is the dominant effect in how much current flows from the drain (D) to the source (S), or vice-versa. When the gate turns off the transistor, only negligible amount of leakage current should flow between the drain and source terminals. And in fact, that has been the case up until now. Starting with 28nm transistors, leakage current can no longer be ignored. The minimum allowable gate length has shrunk so much and the physical distance between drain and source so small that even when the transistor is supposedly off, the leakage current is on the same order of magnitude as the active current. Thus, even if you’re not using the chip, it may still draw significant amounts of power. Obviously, this is a problem.

One of the most straightforward ways to get around this problem, one that is being employed at FluxCorp, is to simply not size our transistors that small. Use ones with bigger gate lengths. Only use minimum gate length transistors where it really matters — areas where high speed processing is required. But a lot of what goes on in a chip do not run at maximum speed, and thus, leaky fast transistors need not be employed. This creates a headache for digital designers. Before, they can just use one flavour of digital logic for all of their designs. Now, they have to partition their designs up in order to optimally use fast, medium, and slow logic gates. They need to balance the ever more tricky trade-offs between active power, leakage power, area, and performance.

In not using the smallest possible logic gates available, the era of cramming twice the number of transistors inside the same amount of area, while theoretically possible, is no longer practical, killed by leakage current brought on by relentless miniaturization. Thus, Moore’s Law is violated. Yet, another aspect of Moore’s Law continues to move forward. As the first plot of this post shows, scaling to ever and ever smaller transistors in an exponential fashion remains unabated. As the title says: Moore is Dead, Long Live Moore.


You’ll probably hit the limit at atomic scales. IE: one atom, one bit. I have no idea how they’ll achieve that and I’ve heard thermal effects kill them at 5 nm. But it will end at some point, unless you can get quantum computing working in large scales

But there’s also been lots of spin to keep the marketing hype going, I seem to remember in the late 1980’s early 1990’s the minimum feature size definition was changed to keep moores law on track.

My mind boggles when I think of what IC engineers do & how they keep coming up with new ways to put more onto an IC & I’m always reminded of this when I read your posts and have to stretch my memory back to grad days.

But, whilst we manage to cram Moore? Onto an IC the basic reason behind moores law is long gone. I seem to remember a good IEEE spectrum piece on it a few years back with an interview with Gordon Moore which should be online.

I read a pretty interesting paper out of Taiwan not too long ago entitled “Design theory and fabrication process of 90nm unipolar-CMOS” in which the authors actually used leakage current to their advantage. A special “punchthrough NMOS” (PT NMOS) device was created and used to make CMOS-like logic circuits. To make this new device, the gate oxide was made slightly thicker than their conventional NMOS transistor so that the gate had less control over the transistor.

For a standard inverter the conventional NMOS is placed on the “bottom” with the PT NMOS atop of it. The input is applied to their gates and the output is taken from the node between the two transistors. Obviously, the standard NMOS functions as expect but things get interesting when looking at the puncthrough device. When Vin = 1 the gate of the PT NMOS has just enough control over the device to halt the flow of puncthrough current and the standard NMOS pulls Vout low. When Vin = 0 the high VDS on the PT device forces a puncthrough current to flow pulling Vout high. Since puncthrough does not cause degeneration, the lifetime of the transistors shouldn’t be hampered.

In my opinion, clever tactics like this will help with the continued scaling of transistors.

http://tinyurl.com/3jrtq2o (should link to IEEE Xplore Abstract Page)

It’s an interesting idea. Unforutnately, it would appear this idea didn’t go anywhere; else, we’d be seeing widespread usage of it by now in 28nm.

It’s still a relatively new idea. I guess I should have mentioned that the paper came out September 2, 2010.

I wonder why they wouldn’t try to publish this in a more widely read forum than Silicon Nanoelectronics Workshop. IEDM is typically the place where big papers on device technology are published.

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