So some time back, I did a few blogs about how much I like writing VHDL and what a wonderfully language it is. I also did a bit of an intro for software engineers (don’t worry, you don’t need to read them to see where I’m going here). However, I came under a bit of criticism about what I wrote and my use of the evil STD_LOGIC_ARITH package. OK, I may not be a full-time VHDL engineer but I think there are far too many people being sheep and using the numeric library though peer pressure while not considering true engineering principles.
So first off, let’s get this all straight – I class myself as a embedded electronics design engineer. My day job is all low-level electronics and microcontrollers, no FPGAs. However, I spent a few years working on a VHDL design for a Gigabit Ethernet Card where I looked after chunks of interface logic and did system testing. After that, I spent considerable time working on hobby VHDL projects and do the same from time to time now. No, I don’t have a PhD in VHDL, so don’t shoot me if I’m not word perfect. The other point about my last blogwas that I was trying to encourage people to look at VHDL and take it up. You should also remember I was writing towards software engineers who know their way around C and other languages. I used software terms to make it more understandable. An example of this is in ‘Functions’ as these are executed slightly different in VHDL and C.
So lets look at this whole ‘Sheep Following’ thing then. I feel that after reading a number of blogs, reviews, and articles that people are being told to use the numeric package because of just that – they are told to and not because they have chosen to.
As an electronics engineer, I have learned that you have to select components carefully. You don’t just pick a BAV99 diode just because someone tells you. I spend time looking at the benefits and limits of each device to decide if it will be the best option for my design. I also consider this every time I do a design, not just keep using the same devices over and over again. What if some other device comes along? Should consider it?
I also do the same as a software engineer. I consider what I want to achieve and then apply a strategy that fits my solution. I know that I’m not alone in this; other engineers think as I do. For example, my principle engineer took a large chuck of I2C code that I had written and decided that, for his application, he would not use it and start from scratch. There is nothing wrong with my code – it’s working very well in a customer’s product, just not what he needed.
And so to the VHDL Shepherds: I feel it’s unfair to be telling people to only use the numeric package and to never use std_logic_arith having passed it off as something evil and grotesque to use. Both packages are very well documented, and in VHDL for Logic Synthesis by Andrew Rushton, it explains very well the differences and even talks about issues that pushed the IEEE to bring about the numeric package. I have no intention in explaining the differences here or why I would use std_logic_arith over numeric but to say that people should remember what this language is, what it generates and what these packages each bring. Any engineer should, no must, look into what they are using and decide for themselves which components they feel are the better.
As engineers, it is our duty to select components in an unbiased environment and make these selections based on solid engineering practices. To cave to external pressures makes you nothing more than a sheep following the herd.